Bit per second to Tebibyte per second

A bit represents a single binary choice — 0 or 1 — which is the fundamental quantum of digital information. Every larger unit (byte, kilobit, megabit) is just a multiple of bits. You cannot meaningfully subdivide a binary digit, so bps is the floor of data rate measurement.

LoRaWAN IoT sensors, some RFID readers, and legacy serial ports (RS-232 at 300–9600 baud) still deal in raw bps ranges. Satellites communicating with deep-space probes also use very low bps — NASA's Voyager 1 transmits at about 160 bps from interstellar space.

Not exactly. Baud measures symbol changes per second, while bps measures bits per second. If each symbol encodes one bit, they are equal. But modern modems encode multiple bits per symbol — a 2400-baud modem using 16-QAM transmits 9600 bps because each symbol carries 4 bits.

Research suggests human speech carries about 39 bits per second of actual information content, regardless of language. Italian speakers talk faster but convey less information per syllable than Japanese speakers, balancing out to roughly the same bps across all studied languages.

The 56 kbps limit came from the Shannon-Hartley theorem applied to analogue phone lines. The 3.1 kHz bandwidth of a voice telephone channel, combined with its signal-to-noise ratio, creates a theoretical ceiling near 56 kbps. FCC power regulations further capped actual downstream to 53.3 kbps.

AMD's MI300X stacks 8 HBM3 memory modules and multiple compute chiplets on a single package using advanced 2.5D packaging with silicon interposers. The short physical distance between compute and memory dies — millimeters instead of centimeters — dramatically reduces signal latency and power per bit. This allows a 5.3 TB/s aggregate bandwidth that would be physically impossible with traditional socketed memory. The trend toward chiplet packaging is how the industry keeps scaling bandwidth despite hitting limits in single-die manufacturing.

Significantly. When provisioning an AI training cluster with hundreds of GPUs, a 10% bandwidth miscalculation cascades through the entire system design — buffer sizes, interconnect capacity, cooling, and power. Getting the units wrong could mean the difference between a training run finishing in 30 days vs 33 days.

Training large language models (100B+ parameters), molecular dynamics simulations, weather modeling, and fluid dynamics at scale. These workloads move enormous matrices through memory billions of times. The TiB/s memory bandwidth of modern GPUs is what makes training models like GPT-4 possible in months rather than decades.

Memory bandwidth dwarfs network bandwidth. Each H100 GPU has 3.35 TiB/s of internal memory bandwidth but connects to the network at only 0.05 TiB/s (400 Gbps InfiniBand). This 60:1 ratio is why AI chip designers obsess over keeping computations local to each GPU and minimising network communication.

Not in the same way. Quantum computers process information through qubits that exist in superposition, so they do not shuttle classical data around at TiB/s. However, the classical control systems that manage quantum processors and process measurement results do need high bandwidth — current quantum-classical interfaces operate at modest Gbps rates.