Word to Mebibit

A word's size depends on the CPU architecture. In x86/x64 (Intel/AMD) documentation: word = 16 bits, DWORD = 32 bits, QWORD = 64 bits. In ARM 32-bit: word = 32 bits. In most modern 64-bit systems (excluding x86 documentation): word = 64 bits. When reading technical documentation, always check the architecture's definition, as "word" is not a universal fixed size.

In Windows API documentation and x86 architecture, a DWORD (Double Word) = 32 bits = 4 bytes, capable of holding values 0–4,294,967,295 (unsigned) or -2,147,483,648 to 2,147,483,647 (signed). DWORD is the most common fixed-width integer type in the Windows API, used for flags, handles, and return codes. The equivalent in modern C/C++ is uint32_t (unsigned) or int32_t (signed).

A CPU's word size determines: (1) the maximum addressable memory — a 32-bit CPU addresses up to 4 GiB (2³² bytes); a 64-bit CPU addresses up to 16 EiB (2⁶⁴ bytes); (2) the precision of integer arithmetic — a 64-bit word handles numbers up to ~18.4 × 10¹⁸ in a single instruction; (3) performance — operations on data smaller than the word size may require extra sign-extension instructions on some architectures.

Modern x86-64 CPUs (Intel Core, AMD Ryzen) have 64-bit general-purpose registers, so their native word size is 64 bits for most operations. However, x86 documentation maintains the legacy definition: "word" = 16 bits, DWORD = 32 bits, QWORD = 64 bits. This creates a confusing terminology mismatch between the architectural naming convention and the physical register size.

Memory alignment means storing data at addresses that are multiples of the data's size. A 32-bit word should be stored at an address divisible by 4 (bytes); a 64-bit word at an address divisible by 8. Misaligned access is either forbidden (causes a CPU fault) or penalised (requires two memory reads instead of one). Compilers automatically align variables; manual struct packing can create misalignment that causes subtle performance issues or crashes on strict architectures.

A megabit (Mb) = 1,000,000 bits (SI decimal). A mebibit (Mibit) = 1,048,576 bits (IEC binary = 2²⁰ bits). The mebibit is 4.857% larger. Network speeds use megabits (Mb); embedded memory and flash storage specifications use mebibits when binary precision is required.

Mebibit appears primarily in microcontroller and microprocessor datasheets (e.g. "2 Mibit flash memory"), FPGA configuration file sizes, and some wireless protocol standards (802.11 frame size limits, Bluetooth payload specifications). It is rarely seen in consumer-facing applications but is common in embedded systems engineering documentation.

Yes. In 2007, a class-action settlement required Western Digital to pay $2.1 million because their hard drives advertised capacity in decimal megabits/gigabits while operating systems reported binary values — making drives appear ~7% smaller than labeled. Similar suits hit Seagate and Samsung. These lawsuits accelerated industry adoption of IEC prefixes and pushed Apple (2009) and later Windows (2021) to clarify their capacity labeling.

SPI flash chips are addressed at the bit level during serial communication — the programr shifts data in one bit at a time over the SPI bus. Datasheets specify capacity in mebibits (e.g. W25Q16 = 16 Mibit = 2 MiB) because the serial interface operates on bits, not bytes. Calculating transfer time requires bit-level math: reading a full 16 Mibit chip at 80 MHz SPI clock takes about 0.2 seconds.

Flash memory chips organise storage in binary-aligned blocks (sectors, pages) whose sizes are powers of 2. Specifying capacity in mebibits (1,048,576 bits per Mibit) maps precisely to the physical organisation of the memory array. Using decimal megabits would result in non-integer block counts, making datasheet specifications harder to verify against hardware design.