Word to Tebibit

A word's size depends on the CPU architecture. In x86/x64 (Intel/AMD) documentation: word = 16 bits, DWORD = 32 bits, QWORD = 64 bits. In ARM 32-bit: word = 32 bits. In most modern 64-bit systems (excluding x86 documentation): word = 64 bits. When reading technical documentation, always check the architecture's definition, as "word" is not a universal fixed size.

In Windows API documentation and x86 architecture, a DWORD (Double Word) = 32 bits = 4 bytes, capable of holding values 0–4,294,967,295 (unsigned) or -2,147,483,648 to 2,147,483,647 (signed). DWORD is the most common fixed-width integer type in the Windows API, used for flags, handles, and return codes. The equivalent in modern C/C++ is uint32_t (unsigned) or int32_t (signed).

A CPU's word size determines: (1) the maximum addressable memory — a 32-bit CPU addresses up to 4 GiB (2³² bytes); a 64-bit CPU addresses up to 16 EiB (2⁶⁴ bytes); (2) the precision of integer arithmetic — a 64-bit word handles numbers up to ~18.4 × 10¹⁸ in a single instruction; (3) performance — operations on data smaller than the word size may require extra sign-extension instructions on some architectures.

Modern x86-64 CPUs (Intel Core, AMD Ryzen) have 64-bit general-purpose registers, so their native word size is 64 bits for most operations. However, x86 documentation maintains the legacy definition: "word" = 16 bits, DWORD = 32 bits, QWORD = 64 bits. This creates a confusing terminology mismatch between the architectural naming convention and the physical register size.

Memory alignment means storing data at addresses that are multiples of the data's size. A 32-bit word should be stored at an address divisible by 4 (bytes); a 64-bit word at an address divisible by 8. Misaligned access is either forbidden (causes a CPU fault) or penalised (requires two memory reads instead of one). Compilers automatically align variables; manual struct packing can create misalignment that causes subtle performance issues or crashes on strict architectures.

A terabit (Tbit) = 10¹² bits (SI decimal). A tebibit (Tibit) = 2⁴⁰ bits = 1,099,511,627,776 bits (IEC binary). Tebibit is 9.95% larger. At enterprise storage scale, this 10% difference has real financial consequences: a storage specification error confusing Tbit with Tibit on a 100-unit deployment results in nearly 10 units' worth of capacity discrepancy.

Tebibits appear in: NAND flash memory die specifications and yield calculations, high-speed fabric interconnect specifications (InfiniBand HDR = 200 Gbit/s), supercomputer storage system designs, and academic papers on distributed storage systems. Consumer applications never display tebibits; the term is confined to engineering and procurement contexts.

Modern 3D NAND stacks 100+ layers of memory cells vertically. A single die from a 232-layer TLC NAND chip can hold about 1 Tibit (128 GiB) raw capacity. Manufacturers measure at the die level in tebibits because binary addressing maps directly to the physical array geometry — each layer, block, and page aligns to powers of 2. A 16-die package thus holds 16 Tibit (2 TiB) before error correction overhead.

Each binary prefix multiplies by 1,024 instead of 1,000. The compounding effect: kibi vs kilo = 2.4% difference, mebi vs mega = 4.9%, gibi vs giga = 7.4%, tebi vs tera = 9.95%, pebi vs peta = 12.6%, exbi vs exa = 15.3%. The difference grows by approximately 2.4% with each prefix step, making precision in naming increasingly important at larger scales.

1 Tibit = 2⁴⁰ bits = 2⁴⁰ / 8 bytes = 2³⁷ bytes = 137,438,953,472 bytes ≈ 137.4 GB (decimal). To convert Tibit to GB: multiply by 137.4. To convert Tibit to GiB: divide by 8 (since 1 Tibit = 0.125 TiB = 128 GiB). The exact value: 1 Tibit = 128 GiB.